LBM=During normal operation., SSE=The SPI controller is disabled., MS=The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
Control Register 1. Selects master/slave and other modes.
| LBM | Loop Back Mode. 0 (During normal operation.): During normal operation. 1 (Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).): Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). |
| SSE | SPI Enable. 0 (The SPI controller is disabled.): The SPI controller is disabled. 1 (The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit.): The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit. |
| MS | Master/Slave Mode.This bit can only be written when the SSE bit is 0. 0 (The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.): The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 1 (The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.): The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. |
| SOD | Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |